1. Field of the Invention
The present invention relates to an apparatus for testing a system-on-chip (SoC), and more particularly to an apparatus for testing a system-on-chip (SoC) based on an Advanced Microcontroller Bus Architecture (AMBA).
2. Description of the Related Art
In recent times, with the increasing development of semiconductor architecture technology, a system-on-chip (SoC) in which an Intellectual Property (IP) system is configured in the form of a single chip.
The above-mentioned system-on-chip (SoC) design has generally used a reusable Intellectual Property IP, resulting in the reduction of a design time.
A system-on-chip (SoC) testing time required for improving reliability of the system-on-chip (SoC) is rapidly increasing in proportion to complexity of the system-on-chip (SoC).
In this case, the system-on-chip (SoC) testing costs are determined by a variety of factors, i.e., the size of a test pattern, an injection time of the test pattern, a test wrapper of a built-in core, a system-on-chip (SoC) Test Access Mechanism (TAM), and a test method.
The most important thing of the system-on-chip (SoC) design is to implement a bus system capable of allowing a plurality of IP cores placed on a single chip to communicate with each other. Recently, the most popular system-on-chip (SoC) system is an Advanced Microcontroller Bus Architecture (AMBA) manufactured by the Advanced RISC Machine (ARM) company.
In order to functionally test the IP cores using the above-mentioned AMBA, a Test Interface Controller (TIC), an External Bus Interface (EBI), and a Test Harness, etc. have been used.
However, in order to inspect the presence or absence of a malfunction caused by a variety of physical defects by functionally testing the IP cores using the AMBA, the system-on-chip (SoC) has a relatively low malfunction inspection rate. In order to solve the above-mentioned problem, a variety of structural tests associated with either a BIST (Built In Self Test) or a scan test have been widely used.
A specific technique capable of maintaining TIC (Test Interface Controller) compatibility and performing the structural test has been proposed by C. Feige et al., who have Published a research paper entitled “Integration of the Scan-Test Method into an Architecture Specific Cote-test Approach” in Journal of Electronic Testing, Volume 14, pp. 125˜131, July 1998, which is incorporated herein by reference.
However, the above-mentioned technique capable of maintaining the TIC compatibility simultaneously while performing the structural test can improve reliability of the AMBA-based system-on-chip (SoC) using the scan test, however, it cannot simultaneously perform the scan input/output functions, such that a test time unnecessarily increases.
In the meantime, a representative example of the above-mentioned technique capable of simultaneously performing the scan input/output functions has been proposed by C. Lin and H. Liang, who have Published a research paper entitled “Bus-Oriented DFT Design for Embedded Cores” in IEEE Asia-Pacific Conference, Volume 1, pp. 561˜563, December 2004, which is incorporated herein by reference.
The above-mentioned technique capable of simultaneously performing the scan input/output functions has used some parts of address buses from the EBI (External Bus Interface) to the outside of the chip as a test response observation path, such that the scan input function and the scan output function are processed in parallel to each other.
However, the above-mentioned technique capable of simultaneously performing the scan input/output functions modifies the APB and the EBI into others, further includes but signals other than the AMBA to perform the test injection and the test response observation, and can be applied to only the testing of the ABP core having a Primary Input (PI) width of 32 bits or less and a Primary Output (PO) width of 26 bits or less.